MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 234

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.35 PWM SM3 Status Register (PWM_SM3STS)
Address: PWM_SM3STS – F300h base + A2h offset = F3A2h
234
Reset
Read
Write
Bit
PWMBFS
PWMXFS
Reserved
Field
Field
RUF
3–2
1–0
15
14
15
0
0
RUF
14
0
These bits determine the fault state for the PWMA output during fault conditions and STOP mode. It may
also define the output state during WAIT and DEBUG modes depending on the settings of
CTRL2[WAITEN] and CTRL2[DBGEN].
00
01
10
11
PWMB Fault State
These bits determine the fault state for the PWMB output during fault conditions and STOP mode. It may
also define the output state during WAIT and DEBUG modes depending on the settings of
CTRL2[WAITEN] and CTRL2[DBGEN].
00
01
10
11
PWMX Fault State
These bits determine the fault state for the PWMX output during fault conditions and STOP mode. It may
also define the output state during WAIT and DEBUG modes depending on the settings of
CTRL2[WAITEN] and CTRL2[DBGEN].
00
01
10
11
This read-only bit is reserved and always has the value zero.
Registers Updated Flag
REF
Output is forced to logic 0 state prior to consideration of output polarity control.
Output is forced to logic 1 state prior to consideration of output polarity control.
Output is tristated.
Output is tristated.
Output is forced to logic 0 state prior to consideration of output polarity control.
Output is forced to logic 1 state prior to consideration of output polarity control.
Output is tristated.
Output is tristated.
Output is forced to logic 0 state prior to consideration of output polarity control.
Output is forced to logic 1 state prior to consideration of output polarity control.
Output is tristated.
Output is tristated.
13
0
PWM_SM3OCTRL field descriptions (continued)
RF
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
CFA1 CFA0 CFB1 CFB0 CFX1 CFX0
PWM_SM3STS field descriptions
11
0
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
5
0
4
0
3
CMPF
Freescale Semiconductor
0
2
0
1
0
0