MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 138

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
VDD
MAXVAL
MINVAL
VSS
SYNC_IN
Figure 5-13. Square Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=1
These examples show that the waveform period is a function of the difference between
MAXVAL and MINVAL, the STEP size, and the update rate as shown here:
Increasing STEP decreases the resolution of the output steps. Increasing the update rate
decreases the waveform period. Varying MINVAL and MAXVAL changes the DC offset
and the amplitude of the waveform.
5.3.3 DAC settling time
Settling time is the interval, within a specified percentage error band, between the time
data is presented to the DAC input to update (change) and the time its analog output
value reaches its final value. Settling time is affected by circuit propagation delay and the
slew rate of the DAC output capability, plus the real load on DAC output.
Approximately 240 ns settling time, which is caused by the DAC conversion glitch, is
needed in the worst case situations when DAC output is internally fed to other modules,
such as comparator inputs. If DAC output is to a package pin, the additional settling time
is affected by the slew rate of an output amplifier and the load on the pin. The maximum
settling time will not exceed 2 microseconds with a maximum output load (3 kohm || 400
pf) when the output swings from minimum output to maximum output or vice-versa.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
138
Freescale Semiconductor