MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 399

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3.6 SPI Word Delay Register (QSPI0_DELAY)
This register is used to control the delay between words.
Address: QSPI0_DELAY – F200h base + 5h offset = F205h
Freescale Semiconductor
Reset
Read
Write
FIFO_ENA
Bit
Reserved
Reserved
RFWM
15–13
WAIT
12–0
Field
Field
3–2
1
0
15
0
14
0
0
Rx FIFO Watermark
These read/write bits determine how many words must be used in the Rx FIFO before an interrupt is
generated. Decreasing the value RFWM increases the allowable latency in servicing the Rx interrupt
without overrunning the Rx buffer space. Smaller values of RFWM may also increase the number of Rx
interrupt service requests because the maximum number of Rx words may not have been used when the
service routine is activated. If RFWM is set to the maximum value then only one SPI word time in interrupt
service latency is allowed before an overrun condition results and receive data is lost.
This field is ignored when FIFO_ENA = 0.
To clear an interrupt generated by RFWM, words must be read from QSPI0_DRCV or the value of RFWM
must be increased.
00
01
10
11
This read-only bit is reserved and always has the value zero.
FIFO Enable
This read/write bit enables Tx and Rx FIFO’s mode.
0
1
This read-only bitfield is reserved and always has the value zero.
Wait Delay
Wait is the 13-bit register that controls the time between data transactions in master mode. The value sets
the number of Peripheral Bus Clocks to delay between words as: (SPWAIT + 1).
FIFO’s are disabled and reset. Operation is compatible with legacy SPI.
FIFO’s are enabled. FIFO’s retain their status even if SPE is set to zero.
Receive interrupt active when Rx FIFO has at least one word used
Receive interrupt active when Rx FIFO has at least two words used
Receive interrupt active when Rx FIFO has at least three words used
Receive interrupt active when Rx FIFO is full
13
0
12
0
QSPI0_FIFO field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
QSPI0_DELAY field descriptions
0
10
0
0
9
Preliminary
0
8
Description
Description
Chapter 12 Queued Serial Peripheral Interface (QSPI)
0
7
WAIT
0
6
0
5
0
4
0
3
0
2
0
1
0
0
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