MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 430

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Register Definition
13.3.3 MSCAN Control Register 1 (CAN_CTL1)
The CAN_CTL1 register provides various control bits and handshake status information
of the MSCAN module
Read: Anytime
Write: Anytime when INITRQ=1 and INITAK=1, except CANE which is write once
when the MSCAN is in initialization mode (INITRQ= 1 and INITAK=1).
Address: CAN_CTL1 – F440h base + 1h offset = F441h
430
Reset
Read
Write
Bit
Reserved
CLKSRC
CANE
15–8
Field
Field
7
6
15
0
14
0
0
1
This read-only bitfield is reserved and always has the value zero.
CAN Enable
Used to enable the CAN
0
1
MSCAN Clock Source
This bit defines the clock source for the MSCAN module (only for systems with a clock generation
module.
0
1
Normal operation
MSCAN in initialization mode
MSCAN module is disabled
MSCAN module is enabled
MSCAN clock source is the oscillator clock
MSCAN clock source is the bus clock
13
0
To protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a
recessive state when the initialization mode is requested by the CPU. Thus, the recommended
procedure is to bring the MSCAN into sleep mode (SLPRQ=1 and SLPAK=1) before requesting
initialization mode.
12
0
CAN_CTL0 field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
CAN_CTL1 field descriptions
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
5
1
4
0
3
Freescale Semiconductor
0
2
SLPA
K
0
1
INITA
K
1
0