MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 613

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

If the clock divider register is written, the DIVLD bit is set automatically. If the DIVLD
bit is zero, the FM_CLKDIV register has not been written since the last reset. If the clock
divider register has not been written, the flash command loaded during a command write
sequence does not execute and the ACCERR flag in the user status register sets.
The clock divider register bits can be modified even after their initialization.
20.3.6 Command Sequence
A command state machine supervises the command processing. To prepare for executing
a command, test the CBEIF flag in the user status register to ensure that the address, data,
and command buffers are empty. Failure to do so may cause the ACCERR bit to set. If
the CBEIF flag is set, the command sequence can be started.
To successfully program flash, follow this command write sequence exactly. Intermediate
writes to the HFM are not permitted between the steps.
The completion of the command operation is indicated when the CCIF flag sets.
The command state machine flags errors in program or erase write sequences by means
of the access error (ACCERR) and protection violation (PVIOL) flags in the HFM user
status register. An erroneous command-write sequence aborts and sets the appropriate
flag. If a flag is set, the user must clear the ACCERR or PVIOL flag before starting
another command write sequence.
Freescale Semiconductor
1. Using a program memory write instruction, write the desired value to the address in
2. Write the numeric code for the command to the command register, which is a
3. To launch the command, clear the CBEIF flag by writing 1. After the CBEIF flag is
flash memory that you wish to program.
buffered register.
cleared, hardware clears the CCIF flag in the user status register, indicating that the
command was successfully launched. Then the CBEIF flag is set again, indicating
that the address, data, and command buffers are ready for a new command write
sequence to begin.
1/F
(maximum value 60 MHz), can result in incomplete
programming or erasure of the flash memory cells.
If the BTS bit in the configuration register is cleared, the
command write sequence must execute from RAM.
BUS
/4) < 5 µs, where F
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
BUS
Preliminary
NOTE
is the system bus clock frequency
Chapter 20 Flash Memory (HFM)
613