MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 599

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.2.1 HFM Clock Divider Register (HFM_CLKD)
This register controls the period of the F
erase algorithms within the flash module. While the flash module operates at the system
bus's frequency, F
generated by dividing the master oscillator clock (MSTR_OSC; refer to the OCCS
chapter) by a prescaler (determined by the PRDIV8 bit) and a divider (determined by the
DIV[5:0] field). F
The PRDIV8 and DIV[5:0] fields must be set with appropriate values before
programming or erasing the flash array.
Freescale Semiconductor
offset (hex)
Address
1D
10
13
14
18
1A
3
4
HFM_TST_SIG
HFM_USTAT
HFM_SECH
HFM_PROT
HFM_SECL
HFM_DATA
Register
HFM_CMD
HFM_IFR_
name
OPT0
System bus clock frequencies below 1 MHz are not supported
by the flash block for program and erase operations.
CLK
CLK
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
does not vary if the system clock is changed.
must operate in the range between 150 kHz and 200 kHz. F
15
15
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
14
14
RESERVED
13
13
12
12
0
Preliminary
CLK
11
11
0
NOTE
clock used for timed events in program and
10
10
9
9
TST_AREA_SIG
PROTECT[15:0]
0
HFMDATA
8
8
w1c
7
7
0
6
6
IFR_OPT0
Chapter 20 Flash Memory (HFM)
w1c
5
5
w1c
4
4
CMD
0
3
3
w1c
2
2
CLK
1
1
SEC
0
is
599
0
0