MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 243

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
EDGCNTB_EN
ONESHOTB
INP_SELB
EDGB1
EDGB0
Field
5–4
3–2
7
6
1
This field represents the water mark level for capture B FIFOs. The capture flags, STS[CFB1] and
STS[CFB0], won’t be set until the word count of the corresponding FIFO is greater than this water mark
level. (FIFO depth is 1)
Edge Counter B Enable
This bit enables the edge counter which counts rising and falling edges on the PWMB input signal.
0
1
Input Select B
This bit selects between the raw PWMB input signal and the output of the edge counter/compare circuitry
as the source for the input capture circuit.
0
1
Edge B 1
These bits control the input capture 1 circuitry by determining which input edges cause a capture event.
00
01
10
11
Edge B 0
These bits control the input capture 0 circuitry by determining which input edges cause a capture event.
00
01
10
11
One Shot Mode B
This bit selects between free running and one shot mode for the input capture circuitry.
0
1
Edge counter disabled and held in reset
Edge counter enabled
Raw PWMB input signal selected as source.
Output of edge counter/compare selected as source.NOTE:When this bitfield is set to 1, the internal
edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0]
and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in
either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one
or both of the capture registers.
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and
capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit
0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then
captures continue indefinitely on the enabled capture circuit.
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture
circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB]
is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of
the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and
CAPTCTRLB[ARMB] is then cleared.
PWM_SM3CAPTCTRLB field descriptions (continued)
Disabled
Capture falling edges
Capture rising edges
Capture any edge
Disabled
Capture falling edges
Capture rising edges
Capture any edge
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
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Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
Description
243