MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 175

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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6.6.2.11 Cascade-Count Mode
If CTRL[CM] is set to '111', the counter's input is connected to the output of another
selected counter. The counter will count up and down as compare events occur in the
selected source counter. This cascade or daisy-chained mode enables multiple counters to
be cascaded to yield longer counter lengths. When operating in cascade mode, a special
high-speed signal path is used between modules rather than the OFLAG output signal. If
the selected source counter is counting up and it experiences a compare event, the counter
will be incremented. If the selected source counter is counting down and it experiences a
compare event, the counter will be decremented.
Up to four counters may be cascaded to create a 64-bit wide synchronous counter. Check
the data sheet to see if there are any frequency limits for cascaded counting mode.
Whenever any counter is read within a counter module, all of the counters' values within
the module are captured in their respective hold registers. This action supports the
reading of a cascaded counter chain. First read any counter of a cascaded counter chain,
then read the hold registers of the other counters in the chain. The cascaded counter mode
is synchronous.
Freescale Semiconductor
//
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void Pulse_Init(void)
{
}
/* TMRA1_CTRL: CM=0,PCS=3,SCS=2,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=5 */
setReg(TMRA1_CTRL,0x0725);
/* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0,
setReg(TMRA1_SCTRL,0x1000);
setReg(TMRA1_CNTR,0x00);
setReg(TMRA1_LOAD,0x00);
setReg(TMRA1_COMP1,0x0004);
/* TMRA1_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,
setReg(TMRA1_CSCTRL,0x00);
setRegBitGroup(TMRA1_CTRL,CM,0x06);
This example uses TMRA1 for one-shot mode counting.
Timer input 3 is used as the primary count source.
Timer input 2 is used for the trigger input.
(See Processor Expert PulseAccumulator bean.)
Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
/* Set up mode */
/* Reset counter register */
/* Reset load register */
/* Run counter */
/* Set up compare 1 register */
Preliminary
Chapter 6 Quad Timer (TMR)
175