MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 39

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 2
Analog-to-Digital Converter (ADC)
2.1
2.1.1 Overview
The analog-to-digital converter (ADC) is one dual 12-bit ADC in which each ADC
converter has a separate voltage reference and control block.
2.1.2 Features
The analog-to-digital (ADC) converter function consists of two separate analog-to-digital
converters, each with eight analog inputs and its own sample and hold circuit. A common
digital control module configures and controls the functioning of the converters. ADC
features include:
Freescale Semiconductor
• 12-bit resolution
• Maximum ADC clock frequency of 15 MHz with 100 ns period
• Sampling rate up to 3.33 million samples per second
• Single conversion time of 8.5 ADC clock cycles (8.5 × 100 ns = 850 ns)
• Additional conversion time of 6 ADC clock cycles (6 × 100 ns = 600 ns)
• Eight conversions in 26.5 ADC clock cycles (26.5 × 100 ns = 2.65 µs) using parallel
• Can be synchronized to the PWM through the SYNC0/1 input signal if the
mode
integration permits the PWM to trigger a timer channel connected to that input
1. In loop mode, the time between each conversion is 6 ADC clock cycles (600 ns). Using simultaneous conversion,
Introduction
two samples can be obtained in 600 ns. Samples per second is calculated according to 600 ns per two samples or
3,333,333 samples per second.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
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