MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 422

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Register Definition
The next table shows the common 13-byte data structure of receive and transmit buffers
for extended identifiers. The mapping of standard identifiers into the IDR registers is
shown in the table after that .
All bits of the receive and transmit buffers are ' x' out of reset because of RAM-based
implementation
read 'x'.
Read: For transmit buffers, anytime when TXEx flag is set and the corresponding
transmit buffer is selected in CAN_TBSEL. For receive buffers, only when RXF flag is
set.
422
2. Exception: The transmit priority registers are 0 out of reset.
Register Name
DSR0
DSR1
DSR2
DSR3
DSR4
DSR5
DSR6
DSR7
IDR0
IDR1
IDR2
IDR3
DLR
Table 13-2. Receive/Transmit Message Buffer — Extended Identifier Mapping
2
. All reserved or unused bits of the receive and transmit buffers always
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
ID28
ID20
ID14
Bit 7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
ID6
ID27
ID19
ID13
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
ID5
6
Preliminary
ID26
ID18
ID12
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB5
ID4
5
SRR (=1)
Blank cell = unused, always read 'x'
ID25
ID11
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB4
ID3
4
IDE (=1)
DLC3
ID24
ID10
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
ID2
3
DLC2
ID23
ID17
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DB2
ID9
ID1
2
Freescale Semiconductor
DLC1
ID22
ID16
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
ID8
ID0
1
DLC0
ID21
ID15
Bit 0
RTR
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
ID7