MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 394

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map Registers
394
SSB_OVER
SPR3
Field
3–0
DS
5
4
This read/write bit enables hardware pulse of the SS_B pin in master mode between words. This bit may
be used alone or in combination with the SS_AUTO to generate the required SS_B signal. Pulses are
generated between words irrespective of the setting of CPHA.
0
1
SS_B Override Register
This read/write bit overrides the internal SS_B signal input from the I/O pad and replaces it with a level
equal to the setting of the SPMSTR bit. This allows the SPI to function in slave mode, CPHA=1, without
commiting a GPIO pin to be tied low. This bit should not be used in multi-slave systems or when CPHA=0.
In master mode a mode fault error can not be generated so this bit should not be used in a multi-master
system.
0
1
SPI Baud Rate Select
4'h0
4'h1
4'h2
4'h3
4'h4
4'h5
4'h6
4'h7
4'h8
4'h9
No SS_B pulse between words.
SS_B output signal is pulsed high between words. This adds 1.5 baud clocks to the total word period.
The idle state of the SS_B is low unless SSB_AUTO is high and then the idle state is high. Do not use
if MODFEN = 1.
SS_B internal module input is selected to be connected to a GPIO pin.
SS_B internal module input is selected to be equal to SPMSTR.
SPR[2:0]
Not Allowed
2 bits data size
3 bits data size
4 bits data size
5 bits data size
6 bits data size
7 bits data size
8 bits data size
9 bits data size
10 bits data size
000
001
010
011
100
101
110
111
QSPI0_DSCTRL field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table 12-6. SPI Master Baud Rate Selection
Table continues on the next page...
BD2X=0
128
256
16
32
64
2
4
8
Preliminary
SPR3=0
Description
BD2X=1
128
256
512
Baud Rate Divisor (BD)
16
32
64
4
8
BD2X=0
16384
16384
16384
1024
2048
4096
8192
512
SPR3=1
Freescale Semiconductor
BD2X=1
16384
16384
16384
16384
1024
2048
4096
8192