MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 540

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
16.2.2 Reset Status Register (SIM_RSTAT)
SIM_RSTAT is updated during any system reset and indicates the cause of the most
recent reset. It also controls whether the COP reset vector or regular reset vector in the
vector table is used. This register is asynchronously reset during power-on reset and
subsequently is synchronously updated based on the level of the external reset, software
reset, or COP reset inputs. It is one-hot encoded, and only one source is ever indicated. If
multiple reset sources assert simultaneously, the highest-priority source is indicated. The
priority from highest to lowest is POR, EXTR, COP_LOR, COP_CPU, and SWR. POR
is always set during a power-on reset, but POR is cleared and EXTR is set if the external
reset pin is asserted or remains asserted after the power-on reset has deasserted.
Address: SIM_RSTAT – F0E0h base + 1h offset = F0E1h
540
Reset
Read
Write
COP_CPU
COP_LOR
Bit
Reserved
EXTR
SWR
15–7
Field
6
5
4
3
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
Software Reset
When set, this bit indicates that the previous system reset occurred as a result of a software reset (write 1
to the SIM_CTRL[SW Rst] bit). SWR is not set if a COP, external, or POR also occurs.
COP CPU Time-out Reset
When set, this bit indicates that the previous system reset was caused when the computer operating
properly (COP) module signaled a CPU time-out reset. COP_CPU is not set if an external reset, POR, or
COP loss of reference reset also occurs. If COP_CPU is set as code starts executing, the COP reset
vector in the vector table is used. Otherwise, the normal reset vector is used.
COP Loss of Reference Reset
When set, this bit indicates that the previous system reset was caused when the computer operating
properly (COP) module signaled a loss of reference clock reset. COP_LOR is not set if an external or
POR also occurred. If COP_LOR is set as code starts executing, the COP reset vector in the vector table
is used. Otherwise, the normal reset vector is used.
External Reset
When set, this bit indicates that the previous system reset was caused by an external reset. EXTR is set
only if the external reset pin is asserted or remains asserted after the power-on reset deasserts.
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
0
SIM_RSTAT field descriptions
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
0
7
SWR
0
6
COP_
CPU
0
5
COP_
LOR
0
4
EXTR POR
0
3
Freescale Semiconductor
1
2
0
1
0
0
0