MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 48

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
48
CHNCFG_L
HLMTIE
EOSIE0
LLMTIE
ZCIE
Field
7–4
11
10
9
8
The ADC must be in a stable power mode prior to SYNC0 input assertion. Refer to the functional
description of power modes for further details.
In "once" scan modes, only a first SYNC0 input pulse is honored. CTRL1[SYNC0] is cleared in this mode
when the first SYNC input is detected. This prevents unintentionally starting a new scan after the first
scan has completed. The CTRL1[SYNC0] bit can be set again at any time including while the scan
remains in process
0
1
End Of Scan Interrupt Enable
This bit enables an EOSI0 interrupt to be generated upon completion of the scan. For looping scan
modes, the interrupt will trigger after the completion of each iteration of the loop.
0
1
Zero Crossing Interrupt Enable
This bit enables the zero crossing interrupt if the current result value has a sign change from the previous
result as configured by the ZXCTRL register.
0
1
Low Limit Interrupt Enable
This bit enables the Low Limit exceeded interrupt when the current result value is less than the low limit
register value. The raw result value is compared to LOLIM[LLMT] before the offset register value is
subtracted.
0
1
High Limit Interrupt Enable
This bit enables the High Limit exceeded interrupt if the current result value is greater than the high limit
register value. The raw result value is compared to HILIM[HLMT] before the offset register value is
subtracted.
0
1
CHCNF (Channel Configure Low) bits
The bits configure the analog inputs for either single ended or differential conversions. Differential
measurements return the max value ((2**12)-1) when the + input is V
0 when the + input is at V
voltage difference between the two signals. Single ended measurements return the max value when the
input is at V
by which the input exceeds V
xxx1
xxx0
xx1x
Scan is initiated by a write to CTRL1[START0] only
Use a SYNC0 input pulse or CTRL1[START0] to initiate a scan
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Inputs = ANA0-ANA1 — Configured as differential pair (ANA0 is + and ANA1 is --)
Inputs = ANA0-ANA1 — Both configured as single ended inputs
Inputs = ANA2-ANA3 — Configured as differential pair (ANA2 is + and ANA3 is --)
REFH
ADC_CTRL1 field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
, return 0 when the input is at V
REFLO
Table continues on the next page...
REFLO
and the - input is at V
.
Preliminary
Description
REFLO
REFH
, and scale linearly between based on the amount
, and scale linearly between based on the
REFH
and the - input is V
Freescale Semiconductor
REFLO
, return