MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 143

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 6
Quad Timer (TMR)
6.1 Overview
Each timer module (TMR) contains four identical counter/timer groups. Each 16-bit
counter/timer group contains a prescaler, a counter, a load register, a hold register, a
capture register, two compare registers, two status and control registers, and one control
register. All of the registers except the prescaler are read/writable. NOTE: This document
uses the terms "Timer" and "Counter" interchangeably because the counter/timers may
perform either or both tasks.
The load register provides the initialization value to the counter when the counter's
terminal value has been reached.
The hold register captures the counter's value when other counters are being read. This
feature supports the reading of cascaded counters.
The capture register enables an external signal to take a "snap shot" of the counter's
current value.
The COMP1 and COMP2 registers provide the values to which the counter is compared.
If a match occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an
interrupt is generated if enabled, and the new compare value is loaded into the COMP1 or
COMP2 registers from CMPLD1 and CMPLD2 if enabled.
The prescaler provides different time bases useful for clocking the counter/timer.
The counter provides the ability to count internal or external events.
Within a timer module (set of four timer/counters), the input pins are shareable.
6.2 Features
The TMR module design includes these distinctive features:
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor
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