MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 271

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

the submodules. The AUX_CLK signal is broadcast from submodule0 and can be
selected as the clock source by other submodules so that the 8-bit prescaler and
MCTRL[RUN] from submodule0 can control all of the submodules.
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by
dividing the IPBus clock frequency by 1-128. The prescaler bits, CTRL[PRSC], select
the prescaler divisor. This prescaler is buffered and will not be used by the PWM
generator until MCTRL[LDOK] is set and a new PWM reload cycle begins or
CTRL[LDMOD] is set.
7.4.2.2 Register Reload Logic
The register reload logic is used to determine when the outer set of registers for all double
buffered register pairs will be transferred to the inner set of registers. The register reload
event can be scheduled to occur every "n" PWM cycles using CTRL[LDFQ] and
CTRL[FULL]. A half cycle reload option is also supported (CTRL[HALF]) where the
reload can take place in the middle of a PWM cycle. The half cycle point is defined by
the VAL0 register and does not have to be exactly in the middle of the PWM cycle.
As illustrated in
Master Reload signal allowing the reload logic from submodule0 to control the reload of
registers in other submodules.
Freescale Semiconductor
AUX_CLK input
(from submod0)
I PB us clock
EX T_CL K
CL K _SEL
reserved
Figure 7-218. Clocking Block Diagram for Each PWM Submodule
Figure 7-219
0
1
2
3
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PSRC
the reload signal from submodule0 can be broadcast as the
prescaler
8 bit
Preliminary
RUN
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
INIT value
Submodule
Clock
Init
16 bit counter
AUX_CLK output
(from submod0 only)
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