MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 165

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.5.13 Timer Channel Enable Register (TMRx_ENBL)
Addresses: TMRA0_ENBL – F000h base + Fh offset = F00Fh
6.6
6.6.1 General
The counter/timer has two basic modes of operation: it can count internal or external
events, or it can count an internal clock source while an external input signal is asserted,
thus timing the width of the external input signal.
Freescale Semiconductor
Reset
Read
Write
• The counter can count the rising, falling, or both edges of the selected input pin.
• The counter can decode and count quadrature encoded input signals.
Bit
Reserved
ENBL
15–4
Field
3–0
Functional Description
15
0
TMRB0_ENBL – F040h base + Fh offset = F04Fh
F020h base + Fh offset = F02Fh
F030h base + Fh offset = F03Fh
F040h base + Fh offset = F04Fh
F050h base + Fh offset = F05Fh
F060h base + Fh offset = F06Fh
F070h base + Fh offset = F07Fh
14
0
This read-only bitfield is reserved and always has the value zero.
Timer Channel Enable
These bits enable the prescaler (if it is being used) and counter in each channel. Multiple ENBL bits can
be set at the same time to synchronize the start of separate counters. If an ENBL bit is set, then the
corresponding channel starts its counter as soon as the CTRL[CM] field has a value other than 0. When
an ENBL bit is clear, the corresponding counter maintains its current value.
0
1
Timer channel is disabled.
Timer channel is enabled. (default)
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
TMRx_ENBL field descriptions
10
0
0
0
9
Preliminary
0
8
Description
0
7
0
6
0
5
0
4
Chapter 6 Quad Timer (TMR)
1
3
1
2
ENBL
1
1
1
0
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