MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 404

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
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12.4.2.4 Transaction Format When CPHA = 0
The following figure shows an SPI transaction in which CPHA is logic zero. The figure
should not be used as a replacement for data sheet parametric information. It assumes 16
bit data lengths and the MSB shifted out first.
Two waveforms are shown for SCLK: one for CPOL = 0 and another for CPOL = 1. The
diagram may be interpreted as a master or slave timing diagram since the serial clock
(SCLK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the
slave, and the MOSI signal is the output from the master. When CPHA = 0, the first
SCLK edge is the MSB capture strobe. Therefore, the slave must begin driving its data
before the first SCLK edge, and a falling edge on the SS pin is used to start the slave data
transaction. The slave SS pin must be toggled back to high and then low again between
each data word transmitted, as shown in the following figure.
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Before writing to the CPOL bit or the CPHA bit, disable the
SPI by clearing the SPI enable bit (SPE).
Figure 12-10. Transaction Format (CPHA = 0)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Freescale Semiconductor