MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 581

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.2.1 COP Control Register (COP_CTRL)
Address: COP_CTRL – F110h base + 0h offset = F110h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
Reserved
CLOREN
CLKSEL
15–10
Field
PSS
9–8
6–5
7
4
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
Prescaler Select
This two bit field determines the value of the clock divider (prescaler). You may divide the source clock by
1, 16, 256, or 1024. Generally, you use a lower prescaler value for lower frequency clock sources, but any
combination of PSS and timeout may be used as long as they yield the desired timeout value.
Restriction: This field can be changed only when CWP is set to zero.
00
01
10
11
This read-only bit is reserved and always has the value zero.
Clock Source Select
This bitfield selects the clock source for the COP counter. Some safety applications require the watchdog
counter to use a clock source different than the system clock.
Restriction: This field can be changed only when CWP is set to zero. It also should be changed only
00
01
10
11
COP Loss of Reference Enable
This bit enables the operation of the COP loss of reference counter.
Restriction: This bit can be changed only when CWP is set to zero.
0
1
COP loss of reference counter is disabled. (default)
COP loss of reference counter is enabled.
13
No division
Divide by 16
Divide by 256
Divide by 1024
Relaxation oscillator output (ROSC) is used to clock the counter (default)
Crystal oscillator output (COSC) is used to clock the counter
IP bus clock is used to clock the counterRestriction:Do not select the IP bus clock to clock the
counter if the application requires the COP to wake the device from stop mode.
Reserved
0
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
when CEN is clear.
11
0
COP_CTRL field descriptions
Table continues on the next page...
10
0
1
9
Preliminary
PSS
1
8
Description
0
0
7
Chapter 18 Computer Operating Properly (COP)
CLKSEL
0
6
0
5
0
4
CSEN
0
3
0
2
CEN
1
1
CWP
0
0
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