MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 208

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
208
Reserved
Reserved
Reserved
LDMOD
PRSC
FULL
Field
9–8
6–4
DT
10
7
3
2
1
0
1
Full Cycle Reload
This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule counter
matches the VAL1 register. Either CTRL[HALF] or CTRL[FULL] must be set in order to move the buffered
data into the registers used by the PWM generators. If both CTRL[HALF] and CTRL[FULL] are set, then
reloads can occur twice per cycle.
0
1
Deadtime
These read only bits reflect the sampled values of the PWMX input at the end of each deadtime.
Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. Reset clears
these bits.
This read-only bit is reserved and always has the value zero.
Prescaler
These buffered read/write bits select the divide ratio of the PWM clock frequency selected by
CTRL2[CLK_SEL].
Reading CTRL[PRSC] reads the buffered values and not necessarily the values currently in effect.
CTRL[PRSC] takes effect at the beginning of the next PWM cycle and only when the load okay bit,
MCTRL[LDOK], is set or CTRL[LDMOD] is set. This field cannot be written when MCTRL[LDOK] is set.
In the bitfield-setting descriptions, f
in the upper left corner of
peripheral clock.
000
001
010
011
100
101
110
111
This read-only bit is reserved and always has the value zero.
Load Mode Select
This read/write bit selects the timing of loading the buffered registers for this submodule.
0
1
This read-only bit is reserved and always has the value zero.
Half-cycle reloads disabled.
Half-cycle reloads enabled.
Full-cycle reloads disabled.
Full-cycle reloads enabled.
Buffered registers of this submodule are loaded and take effect at the next PWM reload if
MCTRL[LDOK] is set.
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK]
being set.
PWM clock frequency = fclk
PWM clock frequency = fclk/2
PWM clock frequency = fclk/4
PWM clock frequency = fclk/8
PWM clock frequency = fclk/16
PWM clock frequency = fclk/32
PWM clock frequency = fclk/64
PWM clock frequency = fclk/128
PWM_SMnCTRL field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Figure
7-2. This clock is also known as the IPBus clock or simply as the
clk
Preliminary
is the clock input to the PWM peripheral clock input, which appears
Description
Freescale Semiconductor