MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 380

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Low-Power Options
start bit and starts counting system clocks until the falling edge at the beginning of data
bit 7 is detected, at which point it stops counting. This count is divided by 8 (for the 8-bit
periods that have passed) and further divided by 16 to provide new RATE[SBR] and
RATE[FRAC_SBR] values. If the data value of the sync field is 0x55, then these new
RATE[SBR] and RATE[FRAC_SBR] values are placed in the baud rate register. Then
the slave is considered synced to the master and further data words are received properly.
If the data value of the sync field isn’t 0x55, then the LIN sync error (STAT[LSE]) bit is
set and subsequent received data bytes should be ignored.
To detect the break character successfully, the initial baud rate for this slave device must
be within 15 percent of the nominal baud rate for the LIN master device.
11.4.6
11.4.6.1 Run Mode
Clearing the transmitter enable or receiver enable bits (CTRL1[TE] or CTRL1[RE])
reduces power consumption in run mode. SCI registers are still accessible when
CTRL1[TE] or CTRL1[RE] is cleared, but clocks to the core of the SCI are disabled.
11.4.6.2 Wait Mode
SCI operation in wait mode depends on the state of CTRL1[SWAI].
380
• If CTRL1[SWAI] is clear, the SCI operates normally when the DSC core is in wait
• If CTRL1[SWAI] is set, SCI clock generation ceases and the SCI module enters a
mode.
power-conservation state when the DSC core is in wait mode. SCI registers are not
accessible. Setting CTRL1[SWAI] does not affect the state of the receiver enable bit,
CTRL1[RE], or the transmitter enable bit, CTRL1[TE].
If CTRL1[SWAI] is set, any transmission or reception in progress stops at wait mode
entry. The transmission or reception resumes when either an internal or external
interrupt brings the DSC out of wait mode. Exiting wait mode via reset aborts any
transmission or reception in progress and resets the SCI.
Low-Power Options
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor