MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 49

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Reserved
SMODE
Field
2–0
3
xx0x
x1xx
x0xx
1xxx
0xxx
This read-only bit is reserved and always has the value zero.
ADC Scan Mode Control
This field controls the ADC module's scan mode. All scan modes use 16 sample slots defined by the
CLIST1-4 registers. A scan is the process of stepping through a subset of these sample slots, converting
the input indicated by a slot, and storing the result. Unused slots may be disabled using the SDIS register.
Input pairs ANA0-1, ANA2-3, ANA4-5, ANA6-7, ANB0-1, ANB2-3, ANB4-5, and ANB6-7 may be
configured as differential pairs using the CHNCFG fields. When a slot refers to either member of a
differential pair, a differential measurement on that pair is made; otherwise, a single ended measurement
is taken on that input. The CTRL*[CHNCFG] fields' descriptions detail differential and single ended
measurement. The SMODE field determines whether the slots are used to perform one long sequential
scan or two shorter parallel scans, each performed by one of the two converters. SMODE controls how
these scans are initiated and terminated. It also controls whether the scans are performed once or
repetitively. For details, refer to
Parallel scans may be simultaneous (CTRL2[SIMULT] is 1) or non-simultaneous. Simultaneous parallel
scans perform the A and B converter scan in lock step using one set of shared controls. Non-
simultaneous parallel scans operate the A and B converters independently, with each converter using its
own set of controls. Refer to the CTRL2[SIMULT] bit's description for details. Setting any sequential mode
overrides the setting of CTRL2[SIMULT].
000
001
010
011
Once (single) sequential — Upon start or an enabled sync signal, samples are taken one at a
time starting with CLIST1[SAMPLE0], until the first disabled sample is encountered. If no disabled
sample is encountered, conversion concludes after CLIST4[SAMPLE15]. If the scan is initiated by a
SYNC signal, only one scan is completed because the CTRL*[SYNC*] bit is cleared automatically
by the initial SYNC detection. CTRL*[SYNC*] can be set again at any time during the scan.
Once parallel — Upon start or an armed and enabled sync signal: In parallel, converter A converts
SAMPLEs 0-3, 8-11, and converter B converts SAMPLEs 4-7, 12-15. When CTRL2[SIMULT] is 1
(default), scanning stops when either converter encounters a disabled sample or both converters
complete all 8 samples. When CTRL2[SIMULT] is 0, a converter stops scanning when it
encounters a disabled sample or completes all 8 samples. If the scan is initiated by a SYNC signal,
only one scan is completed because the CTRL*[SYNC*] bit is cleared automatically by the initial
SYNC detection. CTRL*[SYNC*] can be set again at any time during the scan. If CTRL2[SIMULT]
is 0, the B converter must be rearmed by writing the CTRL2[SYNC1] bit.
Loop sequential — Upon an initial start or enabled sync pulse, up to 16 samples in the order
SAMPLEs 0-15 are taken one at a time until a disabled sample is encountered. The process
repeats perpetually until the CTRL1[STOP0] bit is set. While a loop mode is running, any additional
start commands or sync pulses are ignored unless the scan is paused using the SCTRL[SC*] bits.
If PWR[ASB] or PWR[APD] is the selected power mode control, PWR[PUDELAY] is applied only on
the first conversion.
Loop parallel — Upon an initial start or enabled sync pulse, converter A converts SAMPLEs 0-3,
8-11, and converter B converts SAMPLEs 4-7, 12-15. Each time a converter completes its current
scan, it immediately restarts its scan sequence. This process continues until the CTRL*[STOP*] bit
is asserted. While a loop is running, any additional start commands or sync pulses are ignored
unless the scan is paused using the SCTRL[SC*] bits. When CTRL2[SIMULT] is 1 (default),
scanning restarts when either converter encounters a disabled sample. When CTRL2[SIMULT] is
Inputs = ANA2-ANA3 — Both configured as single ended inputs
Inputs = ANB0-ANB1 — Configured as differential pair (ANB0 is + and ANB1 is --)
Inputs = ANB0-ANB1 — Both configured as single ended inputs
Inputs = ANB2-ANB3 — Configured as differential pair (ANB2 is + and ANB3 is --)
Inputs = ANB2-ANB3 — Both configured as single ended inputs
ADC_CTRL1 field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Sequential Versus Parallel Sampling
Preliminary
Description
Chapter 2 Analog-to-Digital Converter (ADC)
and
Scan
Sequencing.
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