MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 432

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Register Definition
13.3.4 MSCAN Bus Timing Register 0 (CAN_BTR0)
The CAN_BTR0 register configures various CAN bus timing parameters of the MSCAN
module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ=1 and INITAK=1)
Address: CAN_BTR0 – F440h base + 2h offset = F442h
432
Reset
Read
Write
Bit
Reserved
15–8
Field
SJW
BRP
7–6
5–0
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
Synchronization Jump Width
The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can
be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus.
00
01
10
11
Baud Rate Prescaler
These bits determine the time quanta (Tq) clock which is used to build up the bit timing.
BRP5
0
0
0
0
1
:
13
Synchronization Jump Width 1 Tq Clock Cycle
Synchronization Jump Width 2 Tq Clock Cycle
Synchronization Jump Width 3 Tq Clock Cycle
Synchronization Jump Width 4 Tq Clock Cycle
0
12
0
BRP4
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
0
0
0
1
:
0
11
0
CAN_BTR0 field descriptions
BRP3
0
0
0
0
1
:
10
0
Table 13-8. Baud Rate Prescaler
BRP2
0
9
0
0
0
0
1
Preliminary
:
0
8
BRP1
Description
0
0
1
1
1
:
0
7
SJW
BRP0
0
1
0
1
1
0
6
:
0
5
0
4
Prescaler value (P)
0
3
Freescale Semiconductor
BRP
64
1
2
3
4
:
0
2
0
1
0
0