MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 528

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
528
External Clock Source
External Clock Source
Relaxation Oscillator
Relaxation Oscillator
Relaxation Oscillator
Clock Source
Clock Source
Table 15-9. Clock Choices Without Crystal Oscillator
Table 15-10. Clock Choices with Crystal Oscillator
Clock Selected Configuration Steps
Clock Selected Configuration Steps
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Postscaler
Postscaler
Postscaler
(continued)
Direct
Direct
Table continues on the next page...
Default.
1. Change TRIM as needed to obtain the desired clock rate
2. Change COD, if desired
3. Enable the PLL (PLLPD=0)
4. Wait for PLL lock (LCK1=1 and LCK0=1)
5. Change ZSRC to select the postscaler clock (ZSRC=10).
1. The clock source (CLKIN) should be enabled in the GPIO and SIM
2. Select CLKIN as the source clock (PRECS=1, EXT_SEL=1).
3. Wait 6 NOP's for the synchronizing circuit to change clocks.
4. The relaxation oscillator can be powered down (ROPD=1) to con‐
1. The clock source (CLKIN) should be enabled in the GPIO and SIM
2. Select CLKIN as the source clock (PRECS=1, EXT_SEL=1).
3. Wait 6 NOP's for the synchronizing circuit to change clocks.
4. The relaxation oscillator can be powered down (ROPD=1) to con‐
5. Change COD, if desired
6. Enable the PLL (PLLPD=0)
7. Wait for PLL lock (LCK1=1 and LCK0=1)
8. Change ZSRC to select the postscaler clock (ZSRC=10).
1. The crystal oscillator should be powered down (CLK_MODE=1) to
2. Change TRIM as needed to obtain the desired clock rate
1. The crystal oscillator should be powered down (CLK_MODE=1) to
2. Change TRIM as needed to obtain the desired clock rate
3. Change COD, if desired
4. Enable the PLL (PLLPD=0)
5. Wait for PLL lock (LCK1=1 and LCK0=1)
6. Change ZSRC to select the postscaler clock (ZSRC=10).
Preliminary
as necessary.(Chip dependent)
serve power.
as necessary.(Chip dependent)
serve power
conserve power. Default state
conserve power.
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