MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 324

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
10.3.2 I2C Frequency Divider register (I2Cx_FREQDIV)
Addresses: I2C0_FREQDIV – F210h base + 1h offset = F211h
324
Reset
Read
Write
Bit
Reserved
Reserved
MULT
15–8
Field
Field
ICR
7–6
5–0
0
15
0
I2C1_FREQDIV – F220h base + 1h offset = F221h
14
0
Contains the slave address used by the I2C module when it is addressed as a slave. This field is used in
the 7-bit address scheme and the lower seven bits in the 10-bit address scheme.
This read-only bit is reserved and always has the value zero.
This read-only bitfield is reserved and always has the value zero.
The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate
the I2C baud rate.
00
01
10
11
Clock rate
Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate,
the SDA hold time, the SCL start hold time, and the SCL stop hold time. See
for a list of values corresponding to each ICR setting.
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = bus speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C
data).
SDA hold time = bus period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = bus period (s) × mul × SCL start hold value
13
mul = 1
mul = 2
mul = 4
Reserved
0
12
0
I2Cx_ADDR field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
I2Cx_FREQDIV field descriptions
11
0
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
0
7
MULT
0
6
0
5
0
4
I2C Divider and Hold Values
0
3
Freescale Semiconductor
ICR
0
2
0
1
0
0