MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 325

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.3.3 I2C Control Register 1 (I2Cx_CR1)
Addresses: I2C0_CR1 – F210h base + 2h offset = F212h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
IICEN
15–8
IICIE
Field
Field
MST
TX
7
6
5
4
15
0
I2C1_CR1 – F220h base + 2h offset = F222h
14
0
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = bus period (s) × mul × SCL stop hold value
This read-only bitfield is reserved and always has the value zero.
I2C enable
Enables I2C module operation.
0
1
I2C interrupt enable
Enables I2C interrupt requests.
0
1
Master mode select
When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation
changes from master to slave.
0
1
Transmit mode select
Selects the direction of master and slave transfers. In master mode this bit must be set according to the
type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave
this bit must be set by software according to the SRW bit in the status register.
Disabled
Enabled
Disabled
Enabled
Slave mode
Master mode
13
0
I2Cx_FREQDIV field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
I2Cx_CR1 field descriptions
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
0
7
IICIE
0
6
MST
Chapter 10 Inter-Integrated Circuit (I2C)
0
5
TX
0
4
0
3
RSTA
0
0
2
WUE
N
0
1
0
0
0
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