MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 566

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets
The following figure provides a graphic illustration of the details. Note that the
POR_Delay blocks use osc_clk as their time base because other system clocks are
inactive during this phase of reset.
POR resets are extended 64 mstr_osc clocks to stabilize the power supply and clock
source. All resets are subsequently extended for an additional 32 mstr_osc clocks and 64
system clocks as the various internal reset controls are released. Actual duration is
determined by the primary input clock source (mstr_osc) and mstr_2x clock frequency.
566
COP_CPU
COP_LOR
Power on Reset
& PPD
External
RESET_B IN
(active low)
(active low)
COP_CPU
COP_LOR
LVDR
(active low)
EXTR
LVDR
Label
SWR
POR
System Integration Module
(SIM)
reset_b
por_b
External Reset
Power-On-Reset (PS)
COP CPU reset
COP Loss of Reference reset
Low voltage detect reset (PS)
Software reset (SIM)
Source of Reset
pulse shaper
Delay blocks assert immediately and
de-assert of clock cycles. only after the
programmed number of clock cycles.
Delay 32
mstr_osc
clocks
Figure 16-26. Sources of RESET Functional Diagram
combined_rst_b
SW Reset
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
pulse shaper
Delay 32
mstr_osc
clocks
Table 16-28. Sources of Reset
extended_por_b
pulse shaper
Preliminary
Delay 32
sys clocks
clkgen_rst_b
pulse shaper
Delay 32
sys clocks
OCCS
perip_rst_b
core_rst_b
Freescale Semiconductor
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Peripherals
DSC Core
Memory
Sub-system
JTAG
Timing