MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 331

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Addresses: I2C0_SMB_CSR – F210h base + 7h offset = F217h
Freescale Semiconductor
Reset
Read
Write
ALERTEN
Bit
Reserved
SIICAEN
TCKSEL
SHTF1
FACK
SLTF
15–8
Field
7
6
5
4
3
2
15
0
I2C1_SMB_CSR – F220h base + 7h offset = F227h
14
0
This read-only bitfield is reserved and always has the value zero.
Fast NACK/ACK enable
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the
result of receiving data byte.
0
1
SMBus alert response address enable
Enables SMBus alert response address.
0
1
Second I2C address enable
Enables SMBus device default address
0
1
Timeout counter clock select
Selects the clock source of the timeout counter.
0
1
SCL low timeout flag
This bit is set when the SLT register (consisting of the SLT1 and SLT2 registers) is loaded with a non-zero
value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is zero.
0
1
SCL high timeout flag 1
An ACK or NACK is sent on the following receiving data byte
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a
data byte generates a NACK.
Disabled
Enabled
Disabled
Enabled
Bus clock / 64 frequency
Bus clock frequency
No low timeout occurs
Low timeout occurs
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
I2Cx_SMB_CSR field descriptions
11
0
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
FACK
0
7
0
6
Chapter 10 Inter-Integrated Circuit (I2C)
0
5
0
4
SLTF
0
3
SHTF
1
0
2
SHTF
2
0
1
0
0
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