MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 582

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
18.2.2 COP Timeout Register (COP_TOUT)
The value in this register determines the timeout period of the COP counter.
Considerations about setting the timeout value follow:
582
1. TIMEOUT should be written before the COP is enabled. Changing TIMEOUT while
2. After the COP has been enabled:
CWEN
the COP is enabled results in a timeout period that differs from the expected value.
CSEN
CWP
Field
CEN
3
2
1
0
• The recommended procedure for changing TIMEOUT is to disable the COP,
• Alternatively, the CPU can write to TOUT and then write the proper patterns to
write to TOUT, and then re-enable the COP. This procedure ensures that the new
TIMEOUT is loaded into the counter.
CNTR to cause the counter to reload with the new TIMEOUT value.
COP Stop Mode Enable
This bit controls the operation of the COP counter in stop mode.
Restriction: This bit can be changed only when CWP is set to zero.
0
1
COP Wait Mode Enable
This bit controls the operation of the COP counter in wait mode.
Restriction: This bit can be changed only when CWP is set to zero.
0
1
COP Enable
This bit controls the operation of the COP counter. This bit always reads as zero when the chip is in
debug mode.
Restriction: This bit can be changed only when CWP is set to zero.
0
1
COP Write Protect
This bit controls the write protection feature of the COP control register (CTRL) and the COP timeout
register (TOUT). Once set, this bit can be cleared only by resetting the module.
0
1
COP counter stops in stop mode. (default)
COP counter runs in stop mode if CEN is set to one.
COP counter stops in wait mode. (default)
COP counter runs in wait mode if CEN is set to one.
COP counter is disabled.
COP counter is enabled. (default)
The CTRL and TOUT registers are readable and writable. (default)
The CTRL and TOUT registers are read-only.
COP_CTRL field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Description
Freescale Semiconductor