MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 398

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map Registers
398
Reserved
Reserved
Reserved
Reserved
RFCNT
TFCNT
TFWM
14–12
10–8
Field
6–5
15
11
7
4
This read-only bit is reserved and always has the value zero.
These read-only bits show how many words are used in the Tx FIFO. Writes to the QSPI0_DXMIT will
cause TFCNT to increment; as words are pulled for transmission TX_LEVEL will be decremented.
Attempts to write new data to QSPI0_DXMIT will be ignored when TFCNT indicates the FIFO is full. If
FIFO_ENA is set to zero the TFCNT will always indicate FIFO empty. If master mode is enabled then
transmission will continue till the FIFO is empty even if SPE is set to zero.
000
001
010
011
100
This read-only bit is reserved and always has the value zero.
Rx FIFO Level
These read-only bits show how many words are used in the Rx FIFO. As words are received RFCNT will
be incremented; as words are read from the QSPI0_DRCV register the value of RFCNT will be
decremented. There is one word time to read QSPI0_DRCV between when the SPRF status bit is set
(interrupt asserted) and when an overflow condition will be flagged. If FIFO_ENA is set to zero the
RFCNT will always indicate FIFO empty.
000
001
010
011
100
This read-only bit is reserved and always has the value zero.
Tx FIFO Watermark
These read/write bits determine how many words must remain in the Tx FIFO before an interrupt is
generated. Increasing the value of TFWM increases the allowable latency in servicing the Tx interrupt
without underrunning the Tx buffer space. Larger values of TFWM may also increase the number of Tx
interrupt service requests because the maximum number of Tx words may not be available when the
service routine is activated. If TFWM is set to the minimum value then only one SPI word time in interrupt
service latency is allowed before an underrun condition results and continuous transmission is stopped in
master mode or the last data word is re-transmitted in slave mode.
This field is ignored when FIFO_ENA = 0.
To clear an interrupt generated by TFWM, new words must be written to QSPI0_DXMIT or the value of
TFWM reduced.
00
01
10
11
This read-only bit is reserved and always has the value zero.
Transmit interrupt active when Tx FIFO has at least one word used
Transmit interrupt active when Tx FIFO has at least two words used
Transmit interrupt active when Tx FIFO has at least three words used
Transmit interrupt active when Tx FIFO is full
Tx FIFO Empty (If enabled Transmit Empty Interrupt asserted)
One word used in Tx FIFO
Two words used in Tx FIFO
Three words used in Tx FIFO
Tx FIFO Full
Rx FIFO Empty
One word used in Rx FIFO
Two words used in Rx FIFO
Three words used in Rx FIFO
Rx FIFO Full (If enabled Receiver Full Interrupt asserted)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
QSPI0_FIFO field descriptions
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Preliminary
Description
Freescale Semiconductor