MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 327

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Reserved
BUSY
ARBL
IAAS
SRW
IICIF
Field
6
5
4
3
2
1
0
1
Addressed as a slave
The IAAS bit is set when one of the following conditions is met:
This bit sets before the ACK bit does. The CPU needs to check the SRW bit and set TX/RX accordingly.
Writing the I2C Control Register 1 with any value clears this bit.
0
1
Bus busy
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is
detected and cleared when a STOP signal is detected.
0
1
Arbitration lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
0
1
This read-only bit is reserved and always has the value zero.
Slave read/write
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent
to the master.
0
1
Interrupt flag
The IICIF bit sets when an interrupt is pending. This bit must be cleared by software, by writing a one to it
in the interrupt routine. One of the following events can set the IICIF bit:
0
1
• The calling address matches the programmed slave address
• GCAEN is set and a general call is received
• SIICAEN is set and the calling address matches the second programmed slave address
• ALERTEN is set and an SMBus alert response address is received
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer excluding ACK/NACK bit completes if FACK = 1. An ACK or NACK is sent on the
• Match of slave address to calling address including primary slave address, general call address,
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
Transfer in progress
Transfer complete
Not addressed
Addressed as a slave
Bus is idle
Bus is busy
Standard bus operation.
Loss of arbitration.
Slave receive, master writing to slave
Slave transmit, master reading from slave
No interrupt pending
Interrupt pending
bus by writing 0 or 1 to TXAK after this bit is set in receive mode
alert response address, and second slave address.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
I2Cx_SR field descriptions (continued)
Table continues on the next page...
Preliminary
Description
Chapter 10 Inter-Integrated Circuit (I2C)
327