MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 508

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
14.3.2 Interrupt Nesting
Interrupt exceptions may be nested to allow the servicing of an IRQ with higher priority
than the current exception. The DSC core controls the masking of interrupt priority levels
by setting the I0 and I1 bits in its status register (SR).
The IPIC field of the INTC module's CTRL register reflects the state of the priority level
that is presented to the DSC core.
14.3.3 Fast Interrupt Handling
Fast interrupt processing is described in section 9.3.2.2 of the DSP56800E DSC Core
Reference Manual. The Interrupt Controller recognizes fast interrupts before the core
does.
A fast interrupt is defined (to the INTC) by:
508
1. Setting the priority of the interrupt as level 2, using the appropriate field in the IPR
2. Setting the FIMn register to the appropriate vector number.
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast
I1 (SR[9])
registers.
interrupt.
0
0
1
1
IPIC
00
01
10
11
Table 14-23. Interrupt Mask Bit Settings in Core Status Register
I0 (SR[8])
0
1
0
1
Table 14-24. Interrupt Priority Level Field Settings
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Current Interrupt Priority Level
No interrupt or SWILP
Priorities 2 or 3
Exceptions Permitted
Priorities 0, 1, 2, 3
Priority 0
Priority 1
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Preliminary
Required Nested Exception Priority
Priorities 0, 1, 2, 3
Exceptions Masked
Priorities 1, 2, 3
Priorities 0, 1, 2
Priorities 2, 3
Priorities 0, 1
Priority 3
Priority 0
Freescale Semiconductor
None