MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 447

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.3.19 MSCAN Identifier Acceptance Registers (Second Bank)
On reception, each message is written into the background receive buffer. The CPU is
only signalled to read the message if it passes the criteria in the identifier acceptance and
identifier mask registers (accepted); otherwise, the message is overwritten by the next
message (dropped).
The acceptance registers of the MSCAN are applied on the CAN_IDR0–CAN_IDR3
registers of incoming messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard
identifiers, only the first two (CAN_IDAR0/1, CAN_IDMR0/1) are applied.
These registers can be read anytime and can be modified by writing anytime in
initialization mode (INITRQ=1 and INITAK=1).
Addresses: CAN_IDAR4 – F440h base + 18h offset = F458h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
15–8
Field
7–0
AC
15
0
CAN_IDAR5 – F440h base + 19h offset = F459h
CAN_IDAR6 – F440h base + 1Ah offset = F45Ah
CAN_IDAR7 – F440h base + 1Bh offset = F45Bh
(CAN_IDARn)
14
0
This read-only bitfield is reserved and always has the value zero.
Acceptance Code Bits
AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
CAN_IDARn field descriptions
10
0
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
0
9
Preliminary
0
8
Description
0
7
0
6
0
5
0
4
AC
0
3
0
2
0
1
0
0
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