MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 272

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
7.4.2.3 Counter Synchronization
In the following figure, the 16 bit counter will count up until its output equals VAL1
which is used to specify the counter modulus value. The resulting compare causes a
rising edge to occur on the Local Sync signal which is one of four possible sources used
to cause the 16 bit counter to be initialized with INIT. If Local Sync is selected as the
counter initialization signal, then VAL1 within the submodule effectively controls the
timer period (and thus the PWM frequency generated by that submodule) and everything
works on a local level.
272
Submodule Clock
Master Reload
Mod Compare
Half Compare
FORCE_OUT
Master Reload
EXT_SYNC
Master Sync
FRCEN
LDOK
INIT_SEL
INIT
Figure 7-220. Submodule Timer Synchronization
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
16 bit counter
0
1
2
3
Figure 7-219. Register Reload Logic
(counts
Reload
cycles)
PWM
Logic
Init
RELOAD_SEL
Local Sync
VAL1
Local Reload
Preliminary
comparator
Processing
0
1
16 bit
Logic
Register Reload
Master Reload
(from submod0 only)
Reload opportunity
(to on-chip trigger unit)
Freescale Semiconductor
Master Sync
(from submod0
only)
Mod Compare