MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 119

DSC 64K FLASH 60MHZ 64-LQFP

MC56F8257MLH

Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8257MLH

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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The option of adding an external resistor bridge for the purpose of adding hysteresis to
the comparator and the amount of hysteresis depends on the user’s individual
requirements. Hysteresis can be important in some system designs. In the absence of
hysteresis, the continuous comparison of nearly identical analog inputs may add noise
and waste power by generating high-frequency oscillations at CMPO.
If external hysteresis is added to the comparator, the bridge must be designed to consider
other issues than how much hysteresis is needed. The resistor values must be sufficiently
high so that they do not cause the drive strength of the digital output driver in the CMPO
IO circuitry to be exceeded. Also, if any digital function other than CMPO must operate
on the CMPO pad in the presence of such a bridge, the resistor values must be
sufficiently high so that the IO circuitry can function appropriately in its digital role.
3.6.4 Startup and Operation
In a typical startup sequence, the time required to stabilize COUT is the power-on delay
of the comparators plus the largest propagation delay from a selected analog source
through the analog comparator, windowing function, and filter. The windowing function
has a maximum of 1 peripheral bus clock period delay. Filter delay is specified in the
Low-Pass Filter section.
Interrupts should be disabled during power up, recovery from partial-power-down, and
while re-enabling the module. Failure to do so could result in spurious interrupts.
Freescale Semiconductor
Input 1
Input 2
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Figure 3-29. External Hysteresis Circuit
CMPO
My
Px
Preliminary
I/O Circuitry
COS
Chapter 3 High Speed Comparator (HSCMP)
COUTA
-
+
EXOR
INV = 0
119

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