MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 377

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

For an 8-bit data character, data sampling of the stop bit takes the receiver the following
number of cycles:
9 bit × 16 RT cycles + 10 RT cycles = 154 RT cycles
With the misaligned character shown in the fast data figure, the receiver counts 154 RT
cycles at the point when the count of the transmitting device is:
10 bit × 16 RT cycles = 160 RT cycles
The maximum percent difference between the receiver count and the transmitter count of
a fast 8-bit character with no errors is:
((154-160) / 154) = 3.90%
For a 9-bit data character, data sampling of the stop bit takes the receiver the following
number of cycles:
10 bit × 16 RT cycles + 10 RT cycles = 170 RT cycles
With the misaligned character shown in the fast data figure, the receiver counts 170 RT
cycles at the point when the count of the transmitting device is:
11 bit × 16 RT cycles = 176 RT cycles
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit character with no errors is:
((170-176) / 170) = 3.53%
11.4.4.8 Receiver Wakeup
So that the SCI can ignore transmissions intended only for other receivers in multiple-
receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup
bit, CTRL1[RWU], puts the receiver into a standby state during which receiver interrupts
are disabled.
The transmitting device can address messages to selected receivers by including
addressing information in the initial frame or frames of each message.
Freescale Semiconductor
Receiver
RT Clock
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Figure 11-28. Fast Data
S TO P
Preliminary
Chapter 11 Queued Serial Communications Interface (QSCI)
Da ta S a m p le s
Id le O r Ne xt Fra m e
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