MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 623

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.3 Memory Map
JTAG has no memory-mapped registers.
21.4 Functional Description
The master TAP consists of a synchronous finite 16-bit state machine, an eight-bit
instruction register, a bypass register, and an identification code register.
21.4.1 JTAG Port Architecture
The TAP controller is a simple state machine used to sequence the JTAG port through its
varied operations:
A block diagram of the JTAG port is provided in Figure 20-1. The JTAG port has four
read/write registers:
Access to the EOnCE registers is described in the device data sheet.
Freescale Semiconductor
• Serially shift in or out a JTAG port command.
• Update and decode the JTAG port Instruction Register (IR).
• Serially input or output a data value.
• Update a JTAG port or EOnCE module register.
• Instruction Register (JTAGIR)
• Chip Identification (CID) register
• Bypass Register (JTAGBR)
• Boundary Scan Register (BSR)
The JTAG port supervises the shifting of data into and out of
the EOnCE module through the TDI and TDO pins,
respectively. In this case, the shifting is guided by the same
controller used when shifting JTAG information.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
NOTE
Chapter 21 Joint Test Action Group (JTAG) Port
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