MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 554

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
16.2.17 Peripheral Clock STOP Disable Register 2 (SIM_SD2)
Address: SIM_SD2 – F0E0h base + 11h offset = F0F1h
16.2.18 I/O Short Address Location Register (SIM_IOSAHI)
The I/O Short Address Location registers specify the memory referenced through the I/O
short address mode, which allows the instruction to specify the lower 6 bits of the
address. The upper address bits are not directly controllable. SIM_IOSAHI allows limited
control of the full address.
The I/O short address is calculated by concatenating the combined ISAL value with the
6-bit short address from the short address opcode.
554
Reset
Read
Write
Bit
PWMCH0
PWMCH1
PWMCH2
PWMCH3
Reserved
15–4
Field
3
2
1
0
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
PWM Channel 0 IPBus Clock STOP Disable
PWM Channel 1 IPBus Clock STOP Disable
PWM Channel 2 IPBus Clock STOP Disable
PWM Channel 3 IPBus Clock STOP Disable
Each bit enables peripheral clocking during STOP mode to the indicated peripheral provided the
corresponding PCEn bit is set to 1 so that the peripheral clock itself is enabled.
0
1
The corresponding peripheral is not clocked in STOP mode
The corresponding peripheral is clocked in STOP mode
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
SIM_SD2 field descriptions
10
0
0
0
9
Preliminary
0
8
Description
0
7
0
6
0
5
0
4
0
3
Freescale Semiconductor
0
2
0
1
0
0