MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 625

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.4.2.3 TLM_SEL
The TLM_SEL instruction is a user-defined JTAG instruction, disabling the master TAP
and enabling the TAP linking module, or TLM. The TLM then selects the DSC core TAP
or the master TAP as the enabled TAP.
21.4.2.4 TAP Controller
The TAP controller is a synchronous 16-bit finite state machine illustrated in the
following figure. The TAP controller responds to changes at the TMS and TCK pins.
Transitions from one state to another occur on the rising edge of TCK. The value shown
adjacent to each state transition represents the signal present on TMS at the time of a
rising edge of TCK.
The TDO pin remains in the high impedance state except during the shift-DR and shift-IR
TAP controller states. In shift-DR and shift-IR controller states, TDO updates on the
falling edge of TCK. TDI is sampled on the rising edge of TCK.
The TAP controller executes the last instruction decoded until a new instruction is
entered at the update-IR state, or test-logic-reset is entered.
Freescale Semiconductor
0
1
Test-Logic-Reset F
Test-Logic-Reset F
0
Figure 21-3. TAP Controller State Diagram
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
1
0 0
1
Select-DR-Scan 7
Preliminary
Capture-DR
Update-DR
Pause-DR
1
Exit1-DR
Exit2-DR
Shift-DR
0
0
1
0
1
1
0
6
2
1
3
0
5
0
0
1
1
Chapter 21 Joint Test Action Group (JTAG) Port
1
0
Select-iR-Scan 4
Capture-IR
Update-IR
Pause-IR
1
Exit1-IR
Exit2-IR
Shift-IR
0
0
1
0
1
1
0 0
E
A
9
B
8
D
0
0
1
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