MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 472

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Modes of Operation
13.4.4
13.4.4.1 Normal Modes
The MSCAN module behaves as described within this specification in all normal system
operation modes.
13.4.4.2 Special Modes
The MSCAN module behaves as described within this specification in all special system
operation modes.
13.4.4.3 Emulation Modes
In all emulation modes, the MSCAN module behaves just like normal system operation
modes as described within this specification.
13.4.4.4 Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive
valid data frames and valid remote frames, but it sends only "recessive" bits on the CAN
bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a
"dominant" bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally
so that the MAC sub-layer monitors this "dominant" bit, although the CAN bus may
remain in recessive state externally.
472
Time Segment 1
Table 13-85. CAN Standard Compliant Bit Time Segment Settings (continued)
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
Modes of Operation
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Time Segment 2
3
4
5
6
7
8
Preliminary
TSEG2
2
3
4
5
6
7
Synchronization Jump Width
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
Freescale Semiconductor
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
SJW