MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 122

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Interrupts
1. T
3.7 Interrupts
The HSCMP module can generate an interrupt on either the rising or falling edge of the
comparator output (or on both edges). The interrupt request is asserted when both the
SCR[IER] bit and the SCR[CFR] bit are set. It is also asserted when both the SCR[IEF]
bit and the SCR[CFF] bit are set. The interrupt is deasserted by clearing either the
SCR[IER] or SCR[CFR] bit for a rising-edge interrupt, or by clearing the SCR[IEF] and
SCR[CFF] bits for a falling-edge interrupt.
122
Mode
6
7
external sample clock. T
PD
represents the intrinsic delay of the analog component plus the polarity select logic. T
EN
1
1
Table 3-23. Comparator Sample/Filter Maximum Latencies (continued)
WE
1
1
SE
0
0
per
FILTER_CNT FILT_PER
is the period of the peripheral bus clock.
> 0x1
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0x1
0x01 -
0x01 -
0xFF
0xFF
Preliminary
Windowed / Re‐
Windowed / Fil‐
sampled mode
tered mode
Operation
T
PD
+ (FILTER_CNT X FILT_PER X T
T
PD
+ (FILT_PER X T
Maximum Latency
SAMPLE
2T
is the clock period of the
Freescale Semiconductor
per
per
) + 2T
1
per
per
) +