MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 524

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
15.5.5 OCCS External Clock Check Reference (OCCS_CLKCHKR)
CLKCHKR and CLKCHKT are used in applications where it is required to verify the
activity of an external clock source or crystal/resonator oscillator before it is selected as
the active system clock source. PRECS must be 0 to use this function.
Address: OCCS_CLKCHKR – F120h base + 5h offset = F125h
524
Reset
Read
Write
REF_COUNT
CHK_ENA
Bit
EXT_SEL
Reserved
TRIM
14–7
Field
Field
9–0
6–0
10
15
15
0
14
0
External Clock In Select
This bit is used to select the source of the external clock input.
PRECS should be 0 before changing the value of EXT_SEL to avoid glitches on the system clock.
0
1
Internal Relaxation Oscillator TRIM bits
These bits change the size of the internal capacitor used by the internal relaxation oscillator. By testing
the frequency of the internal clock and incrementing or decrementing this factor accordingly, the accuracy
of the internal clock can be improved by 40%. Incrementing these bits by one increases the clock period
by 0.078% of the unadjusted value. Decrementing this register by one decreases the clock period by
0.078%. Reset sets these bits to 200h, centering the range of possible adjustment.
Check Enable
This bit is used to start and stop the clock checking function. Allow enough time after the CLK_ENA is
cleared to allow for two ROSC clock periods before attempting to start another verification cycle.
0
1
This read-only bitfield is reserved and always has the value zero.
Reference Count bits
Use XTAL as the external clock input
Use CLKIN as the external clock input
Writing a low while the clock checking operation is in progress stops the check in it’s current state.
Reading a low after a check has been started indicates that the check operation is complete and the
final values are valid in the REF_CNT and TARGET_CNT registers.
Writing a one clears the REF_CNT and TARGET_CNT registers and starts the clock checking
function. The CLK_ENA bit will remain high while the operation is in progress.
13
0
OCCS_OSCTL field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
OCCS_CLKCHKR field descriptions
11
0
0
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
5
0
4
REF_COUNT
0
3
Freescale Semiconductor
0
2
0
1
0
0