MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 82

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
independently. Each converter has its own start, stop, sync, end-of-scan interrupt enable
controls, and interrupts. Scanning in either converter terminates only when that converter
encounters a disabled sample.
The ADC can be configured to perform a single scan and halt, perform a scan whenever
triggered, or perform the scan sequence repeatedly until manually stopped. The single
scan (once mode) differs from the triggered mode only in that SYNC input signals must
be re-armed after each use and subsequent SYNC inputs are ignored until the SYNC
input is re-armed. This arming can occur any time after the SYNC pulse, including while
the scan is still in process.
Optional interrupts can be generated at the end of a scan sequence. Interrupts are
available simply to indicate that a scan has ended, that a sample is out of range, or several
different zero crossing conditions. Range is determined by the high and low limit
registers.
2.4.1 Input Multiplex Function
The following figure shows the input multiplex function. The ChannelSelect and
SingleEndedDifferential switches are indirectly controlled by settings within the
following registers:
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• CLIST1, CLIST2, CLIST3, CLIST4, and SDIS registers
• CTRL1[CHNCFG_L]
• CTRL2[CHNCFG_H]
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor