MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 429

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
SLPRQ
INITRQ
Field
1
0
NOTE: The CPU has to make sure that the WUPE bit and the WUPIE wake-up interrupt enable bit are
0
1
Sleep Mode Request
This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode. The sleep
mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all
transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK=1. SLPRQ
cannot be set while the WUPIF flag is set. Sleep mode will be active until SLPRQ is cleared by the CPU
or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ
itself.
Note: The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ=1 and
0
1
Initialization Mode Request
Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode.
Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module
indicates entry to initialization mode by setting INITAK=1. The following registers enter their hard reset
state and restore their default values:
The following registers can only be written by the CPU when the MSCAN is in initialization mode
(INITRQ=1 and INITAK=1)
The values of the error counters are not affected by initialization mode. When this bit is cleared by the
CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off
state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off
state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in
CAN_CTL0, CAN_RFLG, CAN_RIER, CAN_TFLG, or CAN_TIER must be done only after initialization
mode is exited, which is INITRQ=0 and INITAK=0.
NOTE: The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ=1
• CAN_CTL0 (excluding WUPE, INITRQ, and SLPRQ bits)
• CAN_RFLG (TSTAT1, TSTAT0, RSTAT1, and RSTAT0 are not affected by initialization mode)
• CAN_RIER
• CAN_TFLG
• CAN_TIER
• CAN_TARQ
• CAN_TAAK
• CAN_TBSEL
• CAN_CTL1
• CAN_BTR0
• CAN_BTR1
• CAN_IDAC
• CAN_IDAR0-7
• CAN_IDMR0-7
Wake-up disabled — The MSCAN ignores traffic on CAN
Wake-up enabled — The MSCAN is able to restart
Running — The MSCAN functions normally
Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
SLPAK=1).
enabled, if the recovery mechanism from stop or wait is required.
and INITAK=1).
CAN_CTL0 field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
Preliminary
Description
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