MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 364

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
1. The address bit identifies the frame as an address character.
11.4.2 Baud-Rate Generation
A 13-bit modulus counter in the baud-rate generator derives the baud rate for both the
receiver and the transmitter. The value written to the RATE[SBR] and
RATE[FRAC_SBR] bits determines the peripheral bus clock divisor. The baud rate clock
is synchronized with the IP Bus clock and drives the receiver. The baud rate clock
divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples
per bit time.
Baud-rate generation is subject to two sources of error:
The following table lists some examples of achieving target baud rates with a peripheral
bus clock frequency of 60 MHz.
364
• Integer division of the peripheral bus clock may not give the exact target frequency.
• Synchronization with the bus clock can cause phase shift.
SBR Bits
Start Bit
390.625
65.125
97.625
195.25
781.25
1562.5
3125
6250
32.5
1
1
1
1
Table 11-22. Example Baud Rates (Peripheral Bus Clock = 60 MHz)
Receiver Clock (Hz)
Table 11-21. Example 9-Bit Data Frame Formats
1,846,154
Data Bits
921,305
614,597
307,298
153,600
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
76,800
38,400
19,200
9,600
9
8
8
8
Transmitter Clock
Preliminary
Address Bit
115,385
1,200.0
57,582
38,412
19,206
9,600
4,800
2,400
600.0
(Hz)
1
0
0
0
1
Target Baud Rate
Parity Bit
115,200
57,600
38,400
19,200
9600
4800
2400
1200
600
0
0
1
0
Freescale Semiconductor
Error (%)
Stop Bit
-0.03
0.16
0.03
0.03
0.00
0.00
0.00
0.00
0.00
1
2
1
1