MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 131

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2.2 Buffered Data Register (DAC_DATA [FORMAT=0])
Address: DAC_DATA [FORMAT=0] – F1A0h base + 1h offset = F1A1h
5.2.3 Buffered Data Register (DAC_DATA [FORMAT=1])
Address: DAC_DATA [FORMAT=1] – F1A0h base + 1h offset = F1A1h
Freescale Semiconductor
Reset
Reset
Read
Read
Write
Write
Bit
Bit
Reserved
15–12
DATA
11–0
Field
PDN
Field
0
15
15
0
0
14
14
0
0
0
1
Power Down
This bit is used to power down the analog portion of the DAC (resulting in its output being pulled low)
when not in use. This bit does not reset the registers and upon clearing of CTRL[PDN] the analog DAC
will output the value currently presented to its inputs. The analog block requires 10 usec to recover from
the power down state before proper operation is guaranteed.
0
1
This read-only bitfield is reserved and always has the value zero.
DAC data (right justified)
Data written to this register is held in a buffer. The digital data contained in this buffer will be presented to
the analog DAC upon the rising edge of the SYNC_IN signal (or at the next clock cycle if
CTRL[SYNC_EN] is clear) and converted to analog and output by the DAC. Reading this register returns
the value being presented to the analog DAC which may differ from the data value being held in the write
buffer. The data in this buffer can be updated at any rate, but the DAC output load impedance may affect
the updating rate.
0
Data words are right justified. (default)
Data words are left justified.
DAC is operational.
DAC is powered down. (default)
13
13
0
0
12
DAC_DATA [FORMAT=0] field descriptions
12
0
0
DAC_CTRL field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
11
0
0
10
10
0
0
DATA
0
0
9
9
Preliminary
0
0
8
8
Description
Description
0
0
7
7
Chapter 5 12-Bit Digital-to-Analog Converter (DAC)
0
0
6
6
DATA
0
0
5
5
0
0
4
4
0
0
3
3
0
0
2
2
0
0
0
1
1
0
0
0
0
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