MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 400

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
12.4
12.4.1
12.4.1.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transactions. With the SPI enabled, software
begins the transaction from the master SPI module by writing to the transmit data
register. If the shift register is empty, the data immediately transfers to the shift register,
setting the SPI transmitter empty bit, SPTE. The data begins shifting out on the MOSI pin
under the control of the SPI serial clock, SCLK.
The SPR3, SPR2, SPR1, and SPR0 bits in the SPI registers control the baud rate
generator and determine the speed of the shift register. Through the SCLK pin, the baud
rate generator of the master also controls the shift register of the slave peripheral
As the data shifts out on the MOSI pin of the master, external data shifts in from the slave
on the master’s MISO pin. The transaction ends when the receiver full bit, SPRF,
becomes set. At the same time that SPRF becomes set, the data from the slave transfers to
the data receive register, DRCV. In normal operation, SPRF signals the end of a
transaction. Software clears SPRF by reading the DRCV register. Writing to the SPI data
transmit register, DXMIT, clears the SPTE bit.
The following figure is an example configuration for a full-duplex master-slave
configuration. Having the SS bit of the master DSC held high is only necessary if
MODFEN = 1. Tying the slave DSC SS bit to ground should only be done if CPHA = 1.
400
Functional Description
Operating Modes
Configure the SPI module as master or slave before enabling
the SPI. Enable the master SPI before enabling the slave SPI.
Disable the slave SPI before disabling the master SPI.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Freescale Semiconductor