MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 602

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
20.2.3 HFM Security Register High (HFM_SECH)
This read-only register stores flash security-related information. It is initialized at reset
using the SECH_VALUE from the flash configuration field.
The reset state of the KEYEN bit is loaded from the flash array during reset.
The reset value of the SECSTAT bit is determined by the value loaded into the SEC field
at reset. The value of SECSTAT can be modified at runtime.
602
LBTS
Field
BTS
1
0
BTS Lock Control
This bit is always readable. It may be set only once. When it is set, it cannot be cleared except by reset.
This bit provides additional security for the flash array by disabling writes to the BTS bit.
NOTE: When other bits in this register are written, this bit might also be written accidentally. Be careful
0
1
Enable Branch-To-Self Feature
This feature allows flash program/erase code to execute from flash.
From the time the command is launched, the value of 0xA97F, which is the opcode of the instruction
"Loop: BRA Loop," is available to be read on the data bus. When the program or erase command ends,
the user data is sent immediately on the read data bus.
NOTE: The Branch-to-Self feature should be enabled only during controlled program/erase sequences.
0
1
The BTS bit is writable.
The BTS bit is write-locked.
An access to the flash memory during program/erase returns invalid data and, meanwhile, the
ACCERR flag is not set.
A read to the flash array when it is unavailable due to program/erase operations results in 0xA97F
being placed on the data bus instead of actual flash data. The code 0xA97F corresponds to a
BRANCH TO SELF instruction for the DSC core.
not to set this bit accidentally when modifying other bits.
It should be disabled during normal operation. Failure to do so can result in an inability to recover
from or detect an illegal access. When the HFM begins its program/erase sequence, it no longer
returns reads from flash memory but instead returns A97Fh, which is a Branch-to-Self instruction.
All interrupts to the CPU must be disabled before the BTS is set and remain disabled until BTS is
cleared. Attempting an interrupt while the BTS feature is engaged corrupts the stack. Because
the processor is currently doing no active calculations (due to the BTS), it simply runs in place
until the flash array is available. To enable the Branch To Self, you must first unlock the BTS bit
by loading the BTS Lock Control (LBTS) with 0, using one of the methods previously described.
The BTS feature works only with the program, page erase, and mass erase commands.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
HFM_CR field descriptions (continued)
Preliminary
Description
Freescale Semiconductor