MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 246

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.46 PWM SM3 Capture Compare X Register
Address: PWM_SM3CAPTCOMPX – F300h base + AFh offset = F3AFh
246
Reset
Read
Write
EDGCMPX
EDGCNTX
Bit
ARMX
15–8
Field
Field
7–0
0
15
0
(PWM_SM3CAPTCOMPX)
14
0
1
Arm X
Setting this bit high starts the input capture process. This bit can be cleared at any time to disable input
capture operation. This bit is self-cleared when in one shot mode and one or more of the enabled capture
circuits has had a capture event.
0
1
Edge Counter X
This read-only field contains the edge counter value for the PWMX input capture circuitry.
Edge Compare X
This read/write field is the compare value associated with the edge counter for the PWMX input capture
circuitry.
The process continues indefinitely.If only one of the capture circuits is enabled, then captures
continue indefinitely on the enabled capture circuit.
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No
further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is
enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then
cleared.
Input capture operation is disabled.
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
PWM_SM3CAPTCTRLX field descriptions (continued)
13
0
EDGCNTX
12
0
PWM_SM3CAPTCOMPX field descriptions
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
5
EDGCMPX
0
4
0
3
Freescale Semiconductor
0
2
0
1
0
0