MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 273

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
The Master Sync signal originates as the Local Sync from submodule0. If configured to
do so, the timer period of any submodule can be locked to the period of the timer in
submodule0. The VAL1 register and associated comparator of the other submodules can
then be freed up for other functions such as PWM generation, input captures, output
compares, or output triggers.
The EXT_SYNC signal originates on chip or off chip depending on the system
architecture. This signal may be selected as the source for counter initialization so that an
external source can control the period of all submodules.
If the Master Reload signal is selected as the source for counter initialization, then the
period of the counter will be locked to the register reload frequency of submodule0. Since
the reload frequency is usually commensurate to the sampling frequency of the software
control algorithm, the submodule counter period will therefore equal the sampling period.
As a result, this timer can be used to generate output compares or output triggers over the
entire sampling period which may consist of several PWM cycles. The Master Reload
signal can only originate from submodule0.
The counter can optionally initialize upon the assertion of the FORCE_OUT signal
assuming that CTRL2[FRCEN] is set. As indicated by the preceding figure, this
constitutes a second init input into the counter which will cause the counter to initialize
regardless of which signal is selected as the counter init signal. The FORCE_OUT signal
is provided mainly for commutated applications. When PWM signals are commutated on
an inverter controlling a brushless DC motor, it is necessary to restart the PWM cycle at
the beginning of the commutation interval. This action effectively resynchronizes the
PWM waveform to the commutation timing. Otherwise, the average voltage applied to a
motor winding integrated over the entire commutation interval will be a function of the
timing between the asynchronous commutation event with respect to the PWM cycle.
The effect is more critical at higher motor speeds where each commutation interval may
consist of only a few PWM cycles. If the counter is not initialized at the start of each
commutation interval, the result will be an oscillation caused by the beating between the
PWM frequency and the commutation frequency.
7.4.2.4 PWM Generation
Figure 7-221
illustrates how PWM generation is accomplished in each submodule. In
each case, two comparators and associated VALx registers are utilized for each PWM
output signal. One comparator and VALx register are used to control the turn-on edge,
while a second comparator and VALx register control the turn-off edge.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor
273