MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 255

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.58 Master Control 2 Register (PWM_MCTRL2)
Address: PWM_MCTRL2 – F300h base + C5h offset = F3C5h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
MONPLL
CLDOK
LDOK
15–2
Field
Field
7–4
3–0
1–0
15
0
14
0
NOTE: For proper initialization of MCTRL[LDOK] and MCTRL[RUN], see the description of PWM
0
1
Clear Load Okay
This write only bit is used to clear MCTRL[LDOK]. Write a 1 to this location to clear the corresponding
MCTRL[LDOK]. If a reload occurs with MCTRL[LDOK] set at the same time that MCTRL[CLDOK] is
written, then the reload will not be performed and MCTRL[LDOK] will be cleared. This bit is self clearing
and always reads as a 0.
Load Okay
This read/set field loads CTRL[PRSC] and the INIT, FRACVALx, and VALx registers of the corresponding
submodule into a set of buffers. The buffered prescaler divisor, submodule counter modulus value, and
PWM pulse width take effect at the next PWM reload if CTRL[LDMOD] is clear or immediately if
CTRL[LDMOD] is set. Set MCTRL[LDOK] by reading it when it is logic zero and then writing a logic one to
it. The VALx, FRACVALx, INIT, and CTRL[PRSC] registers of the corresponding submodule cannot be
written while MCTRL[LDOK] is set. MCTRL[LDOK] is automatically cleared after the new values are
loaded, or can be manually cleared before a reload by writing a logic 1 to MCTRL[CLDOK]. This bit
cannot be written with a zero. Reset clears this field.
NOTE: For proper initialization of MCTRL[LDOK] and MCTRL[RUN], see the description of PWM
0
1
This read-only bitfield is reserved and always has the value zero.
Monitor PLL State
These bits are used to control disabling of the fractional delay block when the chip PLL is unlocked and/or
missing its input reference. The fractional delay block requires a continuous 120 MHz clock from the PLL.
If this clock turns off when the fractional delay block is being used, then the outputs of the fractional delay
block can be stuck high or low even if the PLL restarts. When this control bit is set, PLL problems cause
PWM generator disabled.
PWM generator enabled.
Do not load new values.
Load prescaler, modulus, and PWM values.
13
0
initialization.
initialization.
PWM_MCTRL field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_MCTRL2 field descriptions
11
0
Table continues on the next page...
10
0
0
9
Preliminary
0
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
Description
0
7
0
6
0
5
0
4
0
3
0
2
MONPLL
0
1
0
0
255